What is a “fifo overflow”?
Let's recall how components exchange data! (see also Reader types)
Imagine a diagram containing 3 components, with 1 Writer and 2 Readers (whose inputs are of type FifoReader in our example). When the upstream component (the writer) emits data on its output, it stacks the data into a circular buffer associated to the output. The downstream components' inputs read the data from the stack as shown in the picture below:
Assuming that the readers' inputs are of type FifoReader, when a reader requests data on its input, it either:
- falls asleep until a new piece of data arrives: this happens if the reader has already processed all the data from the writer.
- or gets the oldest data from the Fifo that it has not processed yet.
The above picture demonstrates the following situation:
- the Writer component stacks its samples of data in the circular buffer as soon as he can.
- Reader_1 has already read and processed all the available samples that have been emitted by the Writer. Thus, it enters a sleeping state, and will be woken up immediately when the Writer will provide a new piece of data.
- Reader_2 is late for some reason (not enough CPU resources, not enough bandwidth, ...): It has only read and processed the samples 1, 2, 3, and 4, it is now processing sample 5, and trying to catch up. When Reader_2 will have finished with sample 5, it will request a new data, get sample 6, process sample 6, request new data, get sample 7, etc...
Samples 1, 2, 3 and 4 are filled with light gray stripes in the picture to indicate that they have been processed by all the downstream components, and can now be overwritten by the writer without any problems when it reaches the end of the circular buffer.
If the lack of resources for Reader_2 is temporary, the circular buffer read by FifoReader inputs can be used to absorb temporary overloads of downstream components.
If the lack of resources for Reader_2 is permanent and the Writer generates data faster than Reader_2 can process it, after some time the Writer will fill entirely the circular buffer with data that has not been processed by Reader_2, then will have to overwrite such data: this will result in data loss for Reader_2.
When an upstream component (the Writer) overwrites data that has not been processed yet by all the downstream components connected to the output (Reader_1 and Reader_2), Fifo overflow warning messages are generated.
This indicates 2 problems:
- at least one of the downstream components missed data, which is not an expected behaviour for a FifoReader input.
- the downstream components which are late will always process (when they can) the oldest data available in the buffer, hence an induced latency between the components equal to the duration of the buffer.
There are several ways to deal with such a problem :
- the first thing is to identify which component is late and why: lack of computation resources? lack of bandwidth? can it be blocked by any other process?
- if the lack of resources is momentary, you can increase the size of the circular buffer (this is the FifoSize property of the component's output). This will reduce the chances of a data sample be missed by the downstream component. However if the lack of resources is permanent, the downstream component's latency will increase.
- in case of a lack of CPU or bandwidth, a solution can be to reduce the incoming frame rate: edit the properties of the downstream component input and raise the subsampling property (a subsampling of 3 will make the component process one data out of 3 from the buffer). It is also possible to edit the properties of the upstream component output and raise the subsampling property there: the upstream component will provide less data to the buffer, but be aware that this will also reduce the sample rate for other downstream components that may accept a full sample rate.
- otherwise, it is possible to change the input reader type to other kinds than FifoReader, such as LastOrNextReader or Wait4NextReader.